1. Field of the Invention
The present invention relates to a method of fabricating a metal oxide semiconductor. More particularly, the present invention relates to a method for fabricating a metal oxide semiconductor by performing a selective ion implantation process.
2. Description of the Related Art
In the conventional metal oxide semiconductor process, ion implantation processes are performed to adjust threshold voltage and the anti-punch-through effect. However, the dopant is implanted globally into the entire active region, including the area where the source/drain region is subsequently formed. Due to the global ion implantation process, the series resistance and the junction capacitance of the source/drain region are increased. Furthermore, the sidewall of the gate conductive layer is damaged by the reactive ion etching process performed for forming a gate, so that the reliability and the yield of the gate conductive layer are decreased.
FIGS. 1A through 1I are schematic, cross-sectional diagrams used to depict steps in a conventional method for fabricating a metal oxide semiconductor.
Referring to FIG. 1A, a substrate 100 is provided. A pad oxide layer 102 and a mask layer 104 are formed in sequence on the substrate 100.
Referring to FIG. 1B, a patterned photoresist layer 106 is formed on the mask layer 104.
Referring to FIG. 1C, the mask layer 104, the pad oxide layer 102 and the substrate 100 are etched by dry etching; thus, a trench 108 is formed. Then, the photoresist layer 106 is removed.
Referring to FIG. 1D, an insulator layer 110 is formed over the substrate 100 and fills the trench 108. A portion of the insulator layer 110 is removed to expose the mask layer 104 by chemical-mechanical polishing.
Referring to FIG. 1E, the mask layer 104 is removed by wet etching to expose the pad oxide layer 102.
Referring to FIG. 1F, a global ion implantation process is performed by using the insulator layer 110 as a mask. The ion implantation process is performed three times in sequence to form three doped layers 113, 114 and 116, wherein the depths of the three doped layers 113, 114 and 116 are different. The doped layer 113 is used for forming a p-well or an n-well, the doped layer 114 is used for adjusting threshold voltage and the doped layer 116 is used for the anti-punch-through effect. During the second and the third ion implantation processes, the dopant is implanted globally into the entire active region, including the subsequently formed source/drain region, because only the insulator layer 110 is used as a mask. Due to the global ion implantation process, the series resistance and the junction capacitance of the source/drain region are increased.
Referring to FIG. 1G, the pad oxide layer 102 is removed to expose the substrate 100 by anisotropic etching. A gate oxide layer 118 is formed on the substrate 100 by thermal oxidation.
Referring to FIG. 1H, a conductive layer 120 is formed over the substrate 100 by chemical vapor deposition.
Referring to FIG. 1I, a reactive ion etching process is performed to remove a portion of the conductive layer 120, so that a gate conductive layer 120a is formed. However, the sidewall of the gate conductive layer 120a is also damaged during the reactive ion etching process. Thus, the reliability of the gate conductive layer 120a is decreased.